Polymorphism in System Verilog

class packet;
virtual function display();
$display(“inside the base class”);
endfunction
endclass
class small_packet extends packet;
function display();
$display(“inside the child class”);
endfunction
endclass

module tb;
packet p;
small_packet p1;
initial begin;

p1=new();
p=p1;
p1.display();
p.display();

end
endmodule